1. Field of the Invention
The present invention relates to stressed and strained layers in multilayer heterostructures containing silicon and -germanium and more specifically relates to MOS devices formed in such heterostructures.
2. Description of the Related Art
Strained silicon is widely viewed as an important technology for obtaining desired advancements in integrated circuit performance. Biaxial, in-plane, tensile strained silicon exhibits enhanced in-plane electron and hole mobilities leading to improved n-channel and p-channel MOS field effect transistor (FET) performance relative to unstrained silicon. Mobility enhancement results from a combination of reduced effective carrier mass and reduced intervalley (phonon) scattering.
Strained silicon is conventionally obtained by first growing a thick layer of silicon germanium alloy (SiGe) on a silicon substrate. The SiGe layer is grown to a sufficient thickness that the SiGe layer is relaxed to an unstrained condition at its surface. The in-plane lattice parameter of the SiGe surface is similar to that of a bulk crystal of SiGe of the same composition. SiGe alloys have larger lattice parameters than silicon. Hence the relaxed surface of the SiGe layer provides an in-plane lattice parameter larger than that of silicon. A subsequent thin layer of silicon is grown epitaxially on the relaxed surface of the SiGe layer. The thin epitaxial layer of silicon assumes the larger in-plane lattice parameter of the SiGe and grows in a strained state with bonds in the crystal lattice elongated in the growth plane. This approach, sometimes known as substrate-strained silicon or “virtual substrate” technology, grows a thin pseudomorphic layer of silicon on the relaxed surface of a SiGe layer.
The specific in-plane lattice parameter of the relaxed SiGe is a function of its composition (atomic germanium fraction or mole fraction) and the degree of relaxation achieved (ideally 100%). Silicon and germanium have lattice parameters of 5.43 Å and 5.66 Å respectively and, according to Vegard's law, SiGe has a lattice parameter linearly interpolated between these values in proportion to the atomic germanium fraction in its composition. A thin layer of silicon grown epitaxially on the SiGe surface adopts the larger in-plane lattice spacing (the epitaxial growth is pseudomorphic) and hence is under in-plane tensile strain. Ideally, the strained silicon and relaxed SiGe lattices are coherent at their interface and there is an absence of misfit dislocations at that interface. Due to tetragonal distortion, the silicon layer grown on the SiGe layer exhibits a reduced lattice spacing in the orthogonal, out-of-plane direction.
So long as the strained silicon layer does not exceed a “critical thickness” for strain relaxation and some care is taken, the tensile strain is maintained in the strained silicon layer through the various implantation and thermal processing steps typical of CMOS manufacturing.
Strained SiGe has also been widely researched as a channel layer for enhanced mobility p-channel MOS transistors. In-plane hole mobility is significantly improved in a layer of SiGe that is compressively strained in-plane. However, despite much work on SiGe p-channel MOSFETs, such devices have not been introduced to CMOS manufacturing, at least in part due to the difficulty of forming a device quality gate oxide on a layer of SiGe. One approach to resolving this issue is to overlay the SiGe with a thin layer of silicon of sufficient thickness to avoid germanium contamination of the gate oxide interface yet sufficiently thin to minimize the additional contribution to effective gate oxide thickness.
Use of a strained SiGe layer also is known in the semiconductor industry as a method of forming the base layer in npn heterojunction base transistors (HBTs). In HBTs, the purpose of the SiGe base layer is to enhance the emission of minority carriers (electrons) from the emitter into the base. The consequential improvement in emitter efficiency leads to increased current gain and unity gain cut-off frequency (fT) for high frequency (RF) applications. In bipolar transistors with graded SiGe base layers, performance is improved by the built in drift field which reduces the base transit time, leading to improved fT. Any improvement in hole mobility in the p-type SiGe base layer of an npn HBT is of secondary importance to the transistor performance but is likely to be of some benefit in reducing base resistance and hence increasing the RF unity power gain frequency fmax.
The use of relaxed SiGe as a “virtual substrate” to strain a subsequently deposited epitaxial silicon layer inevitably requires acceptance of a very high dislocation density in the SiGe layer because the SiGe relaxation mechanism is plastic in nature. In other words, relaxation in the SiGe layer occurs through the generation of strain-relieving misfit dislocations. A thin SiGe layer on a silicon substrate is not relaxed and exhibits few misfit dislocations. If the SiGe layer is thicker than the “critical thickness,” the strained lattice undergoes plastic deformation and the stress is relieved by the nucleation and propagation of misfit dislocations. Some fraction of misfit dislocations give rise to threading dislocations (at least 104-105 cm−2) which propagate through the overlying strained silicon layer. One current technology, used commercially by Amberwave Systems Corp. of Salem, N.H., grows a thick (thicker than one micron) SiGe layer of graded (increasing) germanium fraction, planarizes the resulting SiGe surface by chemical mechanical polishing (CMP) and grows a thin layer of SiGe of constant composition before it grows the final pseudomorphic strained silicon layer. Growing the layer of constant composition SiGe over the dislocated SiGe layer is intended to localize the misfit dislocations to the deeper SiGe layer. To date this strategy has failed to eliminate propagation of threading dislocations into the subsequently grown strained silicon layer. Threading dislocations represent extended defects and give rise to multiple undesirable consequences in MOSFETs including source/drain Junction leakage, reduction of channel mobility, variability of threshold voltage and enhanced diffusion paths leading to potential drain-to-source shorting in short-channel MOSFETs.
The thick SiGe layer used in the “virtual substrate” technology has a much lower thermal conductivity than silicon. As a result, strained silicon MOSFETs on relaxed SiGe virtual substrates exhibit self heating effects similar to silicon on insulator (SOI) devices. Self heating has deleterious consequences for MOSFET performance such as increased off-state leakage current and mobility reduction leading to reduced drive current.
A thick relaxed SiGe layer tends to have poor surface morphology on which to grow a thin active layer of silicon (which will host the MOSFET channels). This has led to introduction of a CMP step to re-establish a planar surface, adding to cost of virtual substrate production.
The growth of a thick layer (for example, 2-3 microns) of graded SiGe, as used in forming strained silicon substrates according to the conventional process, has significant cost overhead. In addition, because of the degradation of surface morphology inherent in growing a thick plastically relaxed layer, a CMP step is required followed by another epitaxial growth cycle to form a thin, buffer SiGe layer and the final strained silicon layer. The preferred strategies described below with reference to the invention can avoid the costs of forming a thick graded SiGe layer and performing a CMP step. This should represent a 80-90% reduction in substrate processing costs.